Lec 01 - The Devices

The building blocks in digital circuit design are the silicon semiconductor devices, more specifically

1. the diodes

2. the MOS

3. bipolar transistors

In this lecture, or more specifically, in this course, we will focus more on the MOS, but will quickly cover the diodes and bipolar transistors.

The Diode

Although diodes rarely occur directly in the schematic diagrams of present-day digital gates, they are still omnipresent. For instance, each MOS transistor implicitly contains a number of reverse-biased diodes. Diodes are used to protect the input devices of an IC against static charges. Also, a number of bipolar gates use diodes as a means to adjust voltage levels.

Introduction

The diode to be discussed here is a semiconductor pn-junction. The pn-junction diode is the simplest circuit element of the semiconductor devices. Figure 1.1a shows a cross-section of a typical pn-junction.

Figure 1.1 Abrupt pn-junction diode and its schematic symbol

• The p-type material is created by doping the silicon with acceptor impurities (such as boron), which results in the presence of holes as the dominant or majority carriers.

• Similarly, the doping of silicon with donor impurities (such as phosphorus or arsenic) creates an n-type material, where electrons are the majority carriers.

Aluminum contracts provide access to the p- and n-terminals of the device. The circuit symbol of the diode, as used in schematic diagrams, is introduced in Figure 1.1c.

In a semiconductor, there are two types of charge carriers: electrons (with charge of -1.602×10^-19 C) and holes (with charge of +1.602×10^-19 C)

Semiconductors

Unlike metal and insulator, a unique property of semiconductor is that impurities can be added (in a controlled manner) into it. This is called doping and its purpose is:

• to make the material n-type or p-type, and

• to change the material's conductivity (or resistivity), usually is to increase the conductivity.

In other words, we are changing the conductivity by specifically making the material n-type or p-type. For more about the chemistry side of doping, please go here.

Increasing a material's conductivity is equivalent to decreasing its resistivity.

Origin of Current

In electronics, current is just the movement of charged particles (electrons or holes). This movement happens in two main ways: Drift and Diffusion.

1

Drift Current

As explained clearly in the image. There is an external electric field to drive the movement of the electrons and holes to the equilibrium.

2

Diffusion Current

Diffusion happens whenever something spreads out from where it’s concentrated to where it’s not, e.g., from high concentration to low concentration. In other words, diffusion is driven by the difference in concentrations, or the concentration gradient.

Analogy: recall that when we drop an ink into the water, it will start diffusing until it reaches a static state. Similarly here, under the diffusion, there is no external force, the holes and electrons will spontaneously move to the correct region to reach the equilibrium.

The current in all electronic devices originates from either of these two mechanisms.

Origin of Current in different devices

Below is the table summarizing the carrier movement in different devices

Devices	Movement Mechanism in on-state	Type of Carriers
Resistor	Drift	Electrons (Metal) Electrons and holes (Semiconductor)
Diode	Diffusion	Electrons and holes
Bipolar Junction Transistor	Diffusion	Electrons and holes
MOSFET	Drift	Electrons (NMOS) Holes (PMOS)

Operation

Diode (semiconductor pn-junction) is the simplest (2-terminal) and most fundamental nonlinear circuit element.

• It allows a current flow through it easily in one direction (known as the forward direction, V > 0), but not in the opposite direction (known as the reverse direction, V < 0), except for the reverse breakdown region. This is unlike a resistor, which is a linear element that has a linear current-voltage relation.

• Diode can be used as a switch and in a rectifier circuit to convert AC into DC. (CG1111A!)

Forward Bias

• Under forward-bias (V > 0), an external voltage is applied such that the p-type terminal is at a higher (positive) voltage with respect to the n-type terminal.

• The forward current flows through the diode from the p-type side to the n-type side.

• The forward current remains small (around 0 practically) until the cut-in voltage is reached. It then increases quickly with a small increase in the voltage V thereafter.

• With a substantial forward current, the voltage drop across the diode lies in a narrow range. In other words, the voltage drop almost remains constant.

Reverse Bias

• Under reverse-bias, the voltage at p-type is lower than the voltage at n-type.

• The reverse current (around 0) flows through the diode from the n-type sied to the p-type side.

• For reverse bias voltage magnitude, |V| = V_R < V_Z (V_Z is the breakdown voltage), the reverse current is very small and can be treated practically as zero, meaning the diode is equivalent to an open circuit.

Breakdown Region

• Current, while operating in the breakdown region, can be limited by connecting a resistor, $R$, of suitable value in series with the $pn$ junction diode. ($I=\frac{V_{DD}-V_Z}{R}$)

• Operation in the breakdown region does not destroy the diode, provided the current through it is kept below a certain level (because of the resistor in this circuit), such that the power dissipation ($V×I$) is below what the diode can handle.

More under the hood

As we have mentioned above, the pn-junction or the diode is most fundamental circuit element. We can also find pn-junction in the MOSFET transistor. So, it will be good to know what's happening underneath the hood.

Holes and Electrons

The main carrier in n-type material is electron while in p-type material is hole. But we should know that in whatever material, only the electrons can move freely, and the movement of electrons will cause the "effect" of holes are moving also, but actually the movement of holes is caused by the movement of electrons.

Both n-type and p-type material are neutral, by which I mean inside each material, the number of electrons and the number of protons are the same. The underneath principle is that:

p-type — holes

In p-type material, a new intermediate energy-level is created (yellow plate in the image above) slighly above the energy level which is below the gap so that the electrons (blue spheres in the image above) will move up, leaving behind the holes in the lower energy level, making the electrons at the lower energy level free to move around. This can be seen as the holes moving around.

We move some of the original electrons above the yellow plate. And the number of protons and electrons still remain the same.

n-type — electrons

In n-type material, this new intermediate energy level (yellow plate in the image above) is created at the energy level above the gap. And at this level, the electrons (blue spheres in the image above) can flow freely.

Here, both new protons and electrons are created together so that number of protons and electrons are still the same.

Here, the height only shows the energy level of the electrons, not protons. The higher the level is, the higher energy the electrons at that level has.

The electrons moving at the energy level which is above the gap will and only will recombine with the holes at the energy level which is below the gap.

What does the gap here mean?

Just a quick recap about what the gap means. The gap is called the band gap. Basically, the bigger the gap is, the less conductive the material is. In the semiconductor material, the gap is relatively small. Even the gap is small, if we don't dope the semiconductor material, in other words, creating the above yellow plate, it's hard for the electrons to continuously moving freely in the semiconductor material.

• For n-type material, the yellow plate is called donor energy level.

• For p-type material, the yellow plate is called acceptor energy level.

By themselves, a piece of N-type or P-type silicon is just a resistor (a material that conducts electricity). The magic that makes all modern electronics work happens when we join them together to form a pn-junction. This is what creates the special properties of a diode, a transistor, and every computer chip.

The process to create this kind of yellow plate is called doping. But given that, it is still a bit blur to some of you maybe. So, let's use the high school knowledge to further explain what is doping.

1

Conductor

We know that some materials are good conductors, for example, copper. But why are they good conductors? It is because by looking at copper's atomic structure, we see that it has a single electron in its outermost shell.

Suppose our wire is made up of copper. When a power source is applied, this free electron in the copper, under the influence of the external electric field, will move in a specific direction, thus producing an electric current.

2

Semiconductor

There is a type of material whose conductivity lies between the conductor and the insulator. One example is the silicon and its atomic structure is shown as follows,

Silicon's outermost shell can actually hold 8 electrons, but one silicon atom only has 4 at its outermost shell. If we place multiple silicon atoms together, we will find that one silicon atom can share electron pairs with its four surrounding silicon atoms, forming covalent bonds. This is a very stable structure, which binds the electrons very strongly. Therefore, silicon's conductivity is very weak in this state.

3

N-type Doping

But if we dope silicon with the element phosphorus (which is element #15), phosphorus has 5 electrons in its outermost shell, four of which can form covalent bonds with four silicon electrons. The remaining one acts as a free electron, which increases the conductivity of the new material. This type of doping is called n-type doping. Therefore, in n-type material, the charge carriers are electrons.

4

P-type doping

Similarly, if we dope silicon with the element Boron (which has 3 valence electrons), Boron's 3 outermost electrons can form covalent bonds with silicon, but this leaves an incomplete bond, which forms a hole. However, other electrons can move into this hole. Because another electron moved in, it is equivalent to the hole moving to a different location. At this point, the conductivity of this boron-doped silicon will also increase, and this type of doping is called p-type doping. Therefore, in p-type material, the charge carriers are holes.

Now we have seen the basic structure of n-type and p-type material. Let's see some interesting things when we put them together, which is to form the pn-junction.

Depletion region

In the connection between the n-type material and p-type material, the excessive and diffused electrons from the n-type flows to the p-side and recombine with the excessive holes in the p-type side. As a result, some charge carriers (free electrons for the n-type material and holes for the p-type material) are depleted in the region around the junction interface, so this region is called the depletion region.

Recall that in diode/pn-junction, current is formed because of diffusion.

Diffusion in Diode

The depletion region is charged because the diffusion described above will cause the p-side to have more electrons thus showing negative charge and the n-type side to have less electrons thus showing positive charge. This creates an electric field pointing from the positive charge area to the negative charge area, thus providing a force opposing the charge diffusion. When the electric field is sufficiently strong to cease further diffusion of holes and electrons, the depletion region reaches the equilibrium.

Forward and Reverse Bias combined with Diffusion

If we apply lower voltage at the n-side, the external electric field will cancel out the inner electric field, thus the depletion region will be decreased and the external field will help the movement of the electrons, making it easier for the electrons to move from n-side to p-side. This is called forward bias,

Similarly, if we apply higher voltage at n-side, the external electric field will reinforce the inner electric field, thus increasing the depletion region, making it harder for the electrons to move from n-side to p-side. This is called reverse bias.

BJT

Introduction

• Bipolar junction transistor (BJT) is a 3-terminal device made using a single crystal semiconductor (typically silicon), just like the pn-junction diode.

• BJT is made with 3 doped semiconductor regions, namely emitter, base and collector, corresponding to the 3 terminals.

• The "active" region of the BJT is the region under (and including) the emitter.

• BJT is not a symmetrical device, in particular, impurities added to the emitter is at a much higher concentration than that added to collector.

Modes of Operation

The Bipolar Junction Transistor (BJT) has two pn-junctions: the emitter-base junction and the collector-base junction. Each of these junctions can be either forward biased or reverse biased. However, we will not focus on the BJT, as it is not used in CMOS logic circuits.

MOSFETs

The metal-oxide-semiconductor field-effect transistor (MOSFET, or MOS, for short) is certainly the workhorse of contemporary digital design. Its major asset, from a digital perspective, is that is performs very well as a switch with an infinite off-resistance (for |V_GS| < |V_TH|) and a finite on-resistance (for |V_GS| < |V_TH|).

Before moving on, let's make some conventions

1. For MOSFETs, S denotes Source, D denotes drain, G denotes gate, and B denotes the body or subtrate terminals.

2. For simplicity, we assume body (substrate) is shorted to source terminal.

3. Source and drain are physically symmetrical.

4. Majority charge carriers move from source to drain.

5. V_GS: Gate to source voltage. Or the difference between gate voltage and source voltage. (Treat it as a vector in math, so V_GS=-V_SG)

6. V_DS: Drain to source voltage.

7. V_DD: Supply voltage.

8. V_T: Threshold voltage.

Introduction

There are two types of MOSFET: n-channel and p-channel MOSFETs. Or to put it simply, just NMOS and PMOS.

• An n-channel MOSFET or NMOS is made using a p-type single-crystal silicon substrate.

• Heavily doped n⁺-type regions, created in the substrate, form the source and drain regions.

• The metal or polysilicon electrode on top of the thin oxide (dielectric) layer, between the source and drain regions, is called the gate.

• Note that MOSFET has a fourth terminal, which is the substrate or body.

• Source terminal is the source of the carriers that will flow through the channel to the drain terminal.

  • Analogy: In NMOS, we can think the drain terminal as something that sucks the electrons from the source (ground) to the drain. We will use this analogy in the later parts also.

Physical Structure

• Substrate (body): Lightly doped

• Source, Drain: Heavily doped charge wells; symmetric

• Gate oxide (dielectric): Insulator between gate and channel

• Gate: Controls the charge flow (creates the field effect)

• Gate length: the distance between the source and drain regions under the gate

• n-type source/drain

• p-type body (substrate)

• Electrons flow from source to drain

• Current flows from drain to source

• We can memorize it using "npn".

• Source and body are usually connected to ground (0V)

• V_T is positive.

• When V_GS $\geq$ V_T, device is on.

• Linear region of operation: 0 < V_DS < V_GS - V_T

• V_Dsat = V_GS - V_T

• p-type source/drain

• n-type body (substrate)

• Holes flow from source to drain

• Current flows from source to drain

• Similarly, we can memorize it using "pnp"

• Source and body are usually connected to V_DD

• Drain is not usually connected to ground (0V).

• V_T is negative.

• When V_GS $\leq$ V_T, device is on.

• Linear region of operation: 0 > V_DS > V_GS - V_T

• V_Dsat = V_GS - V_T

Notes

1. The threshold voltage, V_T, is the gate-source voltage at which channel is formed.

   1. The channel in a MOSFET is the path that allows current to flow between the source and the drain — under the gate oxide layer. It forms inside the semiconductor substrate (usually silicon) when we apply a voltage to the gate.

2. For the sake of simplicity, we made the following rules when analyzing the MOSFET.

   1. NMOS and PMOS are ON when the |V_GS| > |V_TH| and OFF when |V_GS| |V_TH|

   2. If we increase |V_GS|, the channel will become wider, thus the output current I_D will increase.

   3. For the determine the linear region or the saturation region, we must strictly following the following table. The V_GS and V_TH relationship we can use the absolute thinking mentioned above. For the V_DS, V_GS and V_TH, we can use the I-V characteristcs diagram introduced later!

We can understand the condition for the NMOS and then flip all the signs when dealing with PMOS.

For the sake of simplicity, in this course, we will use NMOS as an example. And thus the following sections will be based on NMOS. The PMOS equivalent will be left as an exercise to the reader.

Modes of Operations

We may notice that between the source, drain and the subtrate, there are always pn-junctions (purple area in the image below in this section). This is very important and it affects how our electrons can move.

Cut-off

We start when V_GS = 0 -> no channel is formed for V_DS $\geq$ 0 -> No current flow.

In between cut-off and linear

We then increase V_GS unilt V_GS = V_TH.

So what happens physically is that: At this point of time, n-channel is formed between source to drain. This is because as we increase V_GS, and with the existence of the insulator (oxide), the high voltage applied at V_GS pushes away more holes and attracts more electrons to pile up near the surface of the subtrate under the gate. So the surface of p-subtrate effectively becomes n-type and is said to be inverted leading to formation of n-channel. The gate voltage at which this inversion happens is called Threshold voltage, V_TH. As you may notice, below the newly formed n-channel, the new pn-junction is formed, but in this case, it is in the reverse-biased state.

Linear

After that,

1. we continue increasing V_GS until it is bigger than V_TH. And then we stop increasing V_GS and fix it.

2. Then we slowly increase V_DS but it shouldn't exceed V_GS-V_TH.

So now, as V_DS > 0, and there is an n-channel in between source and drain, as we have written above, the current will flow from drain to source.

At point x along the channel, the voltage is V(x), and the gate-to-channel voltage at that point equals V_GS - V(x). We assume that under linear region, this voltage exceeds the threshold voltage all along the channel. So again, what happens physically here is that:

• Within the NMOS, a conductive n-type channel is formed between the source and drain.

• When V_DS​ (drain-to-source voltage) is small, the entire channel is uniformly formed — electrons can move easily.

• As V_DS​ increases slightly, the electric field pushes more electrons, and current I_D​ increases proportionally (Ohm's law). This is valid only for small values of V_DS.

• This is called linear region or resistive region of a MOSFET.

"Region" means a range of V_GS and V_DS values where the MOSFET shows a specific physical behavior and current-voltage or I-V relationship.

In between linear and saturation

Now, as we have already fixed the V_GS and start increasing the V_DS, we increase V_DS until V_DS = V_GS-V_TH. As the value of drain-source voltage V_DS is further increased, the assumption that the channel voltage is larger than the threshold all along the channel ceases to hold. This happens when V_GS - V(x) < V_TH. At that point, the induced charge is zero, and the conducting channel disappears or is pinched-off.

So, what happens physically now? The effective voltage between gate and source V_GD = V_G - V_D = V_GS - V_DS (As V_S = 0) = V_GS - (V_GS - V_TH) = V_TH. Then the channel at drain end begins to pinch off.

Using the sucking analogy on the drain side, we can think of it as when we increase V_DS, the drain will suck the electrons more quickly, thus the channel near to the drain will become thinner. As the drain cosumes the electrons that the source provided, this is also why the source pin is called source and the drain is called drain.

Saturation

As we continue increasing V_DS until V_DS > V_GS - V_TH. Let's denote three variables here:

1. $L$ is the channel length

2. $\Delta L$ is pinched-off channel length

3. $L_{\text{eff}}$ is the effective channel length = $L-\Delta L$

So, what happens physically? Although the channel at the drain end pinches off, the electrons still flow to drain under the influence of high electric field in the pinch-off region from drain to source and hence the current is constant.

Here, in the pinched-off region near the drain, there is still n-channel, it's just that it is very thin, it doesn't mean that there is no n-channel.

What are the short channel effects?

Basically, when transistors get very tiny, the gate loses some control over the channel, and new unwanted effects appear — those are called short-channel effects (SCEs).

---

In summary, we have the following table summarizing the above 5 stages of NMOS.

Condition / VDS Range	Region	Channel Description	Current Behavior / Equation
$V_{GS} < V_{TH}$	Cutoff (OFF)	No inversion channel formed; MOSFET is OFF	$I_D \approx 0$
$V_{GS} \approx V_{TH}$	Boundary between Cutoff and Linear	Channel just starts to form (weak inversion); small leakage current begins	$I_D$ rises exponentially with $V_{GS}$ (subthreshold conduction)
$V_{GS} > V_{TH}$ and $0 < V_{DS} < V_{GS} - V_{TH}$	Linear (Ohmic)	Channel fully formed and uniform; acts like voltage-controlled resistor	$I_D =f(V_{DS}, V_{GS})$
$V_{DS} = V_{GS} - V_{TH}$	Boundary between Linear and Saturation	Channel begins to pinch off at the drain end	Marks start of current saturation
$V_{GS} > V_{TH}$ and $V_{DS} > V_{GS} - V_{TH}$	Saturation (Active)	Channel pinched off near drain; current nearly constant (independent of $V_{DS}$)	$I_D =f(V_{GS})$

In NMOS, why the current only flows from drain to source?

We can think of the three possible routes that the current might flow:

1. Gate to other places: This is not possible as there is an insulator material (oxide) between gate and source, drain and subtrate)

2. Source to body: This is not possible as the source and body are both connected to ground (0V). And because of the existence of the depletion region. No voltage difference plus the depeltion region, the current cannot flow from source to body.

3. Drain to body: As body is 0V and drain is connected to positive voltage, because of the reverse-bias property of the pn-junction, the current cannot flow from drain to body. And as you increase V_DS, the depletion region can only become bigger and bigger, making it even more impossible for the current to flow from the drain to the body.

I-V characteristics

Output characteristic

1

Linear Region

In the linear region, we have two situations

• Increase in V_DS leads to increase in current like voltage-controlled resistor.

• Increase in V_GS leads to a greater number of electrons leading to higher current.

That's why $I_D =f(V_{DS}, V_{GS})$, and the function $f$ is

$$i_D = \mu_n C_{ox} \frac{W}{L} \left[ (V_{GS} - V_T)V_{DS} - \frac{1}{2}V_{DS}^2 \right] \\$$

where

$$\begin{align*} \mu_n & \quad \text{is the electron mobility in the channel} \\ C_{ox} & \quad \text{is the Gate oxide capacitance per unit area} \\ W & \quad \text{is the Channel Width} \\ L & \quad \text{is the Channel length} \end{align*}$$

Based on this equation, we see that $I_D$ doesn't increase perfectly linearly with $V_{DS}$. Only when $V_{DS}$ is very small -> $\frac{1}{2}V_{DS}^2$ is very negligible -> we can say the increasing is linear.

The linear region is where the digital integrated design comes in.

2

Saturation Region

In the saturation region, only the increase in V_GS will affect the current. We denote V_Dsat = (V_GS - V_T).

That's why we have $I_D =f(V_{GS})$, and the function $f$ is

$$i_D = i_{Dsat} = \frac{1}{2}\mu_n C_{ox} \frac{W}{L} (V_{GS} - V_T)^2$$

where,

$$\begin{align*} \mu_n & \quad \text{is the electron mobility in the channel} \\ C_{ox} & \quad \text{is the Gate oxide capacitance per unit area} \\ W & \quad \text{is the Channel Width} \\ L & \quad \text{is the Channel length} \end{align*}$$

The saturation region is where the analog integrated design comes in.

More on Capacitance

1. $C_{ox}=\frac{\epsilon_0\epsilon_r}{t_{ox}}$, where $t_{ox}$ is the thickness of the gate oxide. And sometimes $\epsilon_0\epsilon_r$ will be written as $\epsilon_{ox}$. They are the same.

2. The gate capacitance: $C_{\text{gate}}=C_{ox}\cdot W\cdot L=\frac{\epsilon_{ox}}{t_{ox}}\cdot W\cdot L$.

In summary, below is the NMOS and PMOS I-V characteristics (i_D and V_DS), where the red cicrled part is the linear region and the green circled part is the saturation region. This is called output characteristics, where I_D versus V_DS with V_GS as a parameter.

To put this diagram together, we have the following

From this we can see that, if we fix our V_GS, and increase the magnitude of the V_DS, the PMOS/NMOS will enter the saturation region. Respectively speaking,

1. For NMOS, if we increase V_DS, we will enter the saturation region -> one of the conditions for saturation is V_DS > V_GS - V_TN, which is the same as V_GD < V_TN.

2. For PMOS, if we decrease V_DS, we will enter the saturation region -> one of the conditions for saturation is V_DS < V_GS - V_TP, which is the same as V_GD > V_TP.

Transfer characteristic

If we draw the I-V characteristics between the V_GS and i_D, we will find that after V_GS exceeds beyond V_TH, i_D will increase quadratically as V_GS increases. This is called transferred characteristics, where i_D versus V_GS at a given fixed V_DS value (V_DS is chosen so that the MOSFET is in saturation region).

So, to understand its geometric meaning, we can see from the following graph,

New Transistor Architecture

As for now, we only have one gate to control the channel. Nowadays, the new transistor architecture is called 3D FET.

For example, the following is the diagram showing the height, width and length of FinFET and Gate-All-Around.

FinFet length, width and height

Misc

Timing Diagram

In CG2027, only the following 4 terms will be covered and included in the final test. Thus, knowing how to calculate each of them will be necessary for succeed in this course.

1. t_PHL: output high to low but related to input's effect on output; see the 50% point of V_out and V_in

2. t_PLH: output low to high but related to input's effect on output; also look at the 50% point of V_out and V_in

3. t_f: output high to low, look at output only; 10% and 90% point of V_out

4. t_r: output low to high, look at output only; 10% and 90% point of V_out

Unit Table

In the final, memorize the unit table is necessary for some questions!

Factor	Name	Symbol
10⁹	Giga	G
10⁶	Mega	M
10³	Kilo	k
10²	Hecto	h
10¹	Deca	da
10⁻¹	Deci	d
10⁻²	Centi	c
10⁻³	Milli	m
10⁻⁶	Micro	µ
10⁻⁹	Nano	n
10⁻¹²	Pico	p
10⁻¹⁵	Femto	f
10⁻¹⁸	Atto	a
10⁻²¹	Zepto	z

Homework

Some awesome videos

Great thanks to my tutor juezhao, the following two videos from YouTube explains perfectly on everything under the hood, from the movement of electrons to the pn-junction and then to the MOSFETS.

Besides the above, the following video from bilibili is also awesome!