Lec 02 - CMOS Inverter

Inverter

An inverter can be thought of as a NOT gate. It will negate whatever value from its input.

Ideal Inverter

An ideal inverter has the following V_in-V_out graph (also known as Voltage Transfer Characteristic, or VTC)

From this graph, we can see that

1. When 0 V_in V_DD /2, V_out = V_DD, this means [0, V_DD/2] is Vin's input low range. Similarly, [V_DD/2, V_DD] is Vin's input high range.

   1. NM_H: V_DD /2

   2. NM_L: V_DD /2

   3. Switch threshold: V_DD /2

2. The meaning of gain is just the change rate of V_out with respect to V_in, which is $d\frac{V_{out}}{V_{in}}$

Real Inverter

In the real world, the inverter cannot be that perfect. Its V_in-V_out graph is usually shown as follows

From this graph, we will see some very important conventions used in Electrical Engineering

1. In the V_in-V_out graph, we always treat x-axis as V_in and y-axis as V_out.

2. V_OH: This is the nominal (expected) output voltage when the inverter output is logic HIGH. This is usually around V_DD.

3. V_OL: This is the nominal (expected) output voltage when the inverter output is logic LOW. This is around 0V.

   1. V_OH and V_OL are nominal values, and they are different from the actual output, which we usually define to be just V_out.

   2. Usually, V_OH, V_OL, together with V_IL and V_IH are specified by the manufacturer in the logic family’s datasheet.

4. V_M: This is the switching threshold, where V_in = V_out.

Mapping between Analog and Digital Signals

As analog signals are continuous while digital signals are discrete, when we convert analog signals to digital signals, we need to define some "mappings". In this lecture, the following mapping is defined,

From this graph, we add on to the important conventions that will be used in Electrical Engineering

1. V_IL: The highest input voltage that the gate will still recognize as a logic LOW.

   1. Thus, in this graph, the input low range is [V_OL, V_IL]

2. V_IH: The lowest input voltage that the gate will recognize as a logic HIGH.

   1. Thus, in this graph, the input high range is [V_IH, V_OH]

By definition, V_IH and V_IL are the operational points of the inverter where $\frac{dV_{\text{out}}}{dV_{\text{in}}}=-1$.

Noise Margin

Noise margin is how much noise a signal can tolerate and still be read correctly as 0 or 1. So, in our notation, we can easily treat NM_H as the length of input high range and NM_L as the length of the input low range.

• NM_H = V_OH - V_IH, or more precisely, V_DD - V_IH.

• NM_L = V_IL - V_OL, or more precisely, just V_IL.

Prof. Annie also introduces the following analogy for NM_H and NM_L:

• NM_H defines how much the V_out can drop from the nominal high voltage (V_OH) for it to be read correctly as logic HIGH by the following gate.

• NML defines how much the V_out can go up from the nominal low voltage (V_OL) for it to be read correctly as logic LOW by the following gate.

Fan-in and Fan-out

From the above image, we can clearly see that

1. Fan-out means how many inputs are driven by one output the number of gates that one output signal can drive.

2. Fan-in means how many inputs a gate has, it describes the number of signals feeding into one logic gate.

CMOS Inverter

An inverter can be built using one PMOS and one NMOS shown as follows,

Basic Operation

The basic operations of a CMOS inverter are the same as the inverter. Basically, it's just when input = 0, output = 1 and when input = 1, output = 0. But in this part, we will use the |VGS| thinking to decide the ON/OFF state of the PMOS and NMOS.

1. Input = 0 -> Output = 1: NMOS's |V_GS| = 0 < |V_TH|, NMOS is OFF. PMOS's |V_GS| = V_DD > |V_TH|, PMOS is ON. Thus, V_out is connected to V_DD, output is 1.

2. Input = 1 -> Output = 0: NMOS's |V_GS| = V_DD > |V_TH|, NMOS is ON. PMOS's |V_GS| = 0 < |V_TH|, PMOS is OFF. Thus, V_out is connected to ground, output is 0.

Are V_TH for NMOS and PMOS the same?

As you may notice, we are comparing the |V_GS| with the same |V_TH| in above. This is not a typo! In real world, we do try to make V_TH of PMOS and NMOS the same. This is done by using the sizing technique we have introduced in Tutorial 1 to change the on resistance of the PMOS and NMOS.

Switching Characteristics

As V_in changes, the CMOS inverter goes through five different combinations of regions of operation. These combinations are indicated below:

1. 0 V_in V_TN: NMOS off, PMOS on.

2. V_TN < V_in < V_inv: PMOS linear, NMOS saturation.

3. V_in = V_inv: Both PMOS and NMOS saturation

4. V_inv < V_in < V_DD - |V_TP|: NMOS linear, PMOS saturation

5. V_DD - |V_TP| < V_in V_DD: PMOS OFF, NMOS ON

where,

• V_inv is the switching voltage (same as the V_M we have introduced above)

• V_TN is the threshold voltage of an NMOS.

• V_TP is the threshold voltage of an PMOS.

To understand it more clearly, let's use the following example,

Suppose V_TN = 0.3V, V_TP = -0.3V, V_DD = 1V and V_inv = 0.5V

1. 0 V_in V_TN -> 0 V_in 0.3: Let's take V_in = 0.2V and assume Vout = 1V.

   1. NMOS: |V_GS| < |V_TN|, NMOS is OFF.

   2. PMOS: |V_GS| 0.7V > |V_TP|, PMOS is ON. V_GD = -0.8V < V_TP, PMOS in linear region.

2. V_TN < V_in < V_inv -> 0.4 < V_in < 0.5: Let's take V_in = 0.45V and assume V_out drops a bit but is still high, is 0.9V.

   1. NMOS: |V_GS| > |V_TN|, NMOS is ON. V_GD = -0.45V < V_TN, NMOS operates in saturation region.

   2. PMOS: |V_GS| > |V_TP|, PMOS is ON. V_GD = -0.45V < V_TP, PMOS operates in linear region.

3. V_in = V_inv: Let's say V_in = 0.5V and V_out = 0.5V

   1. NMOS: |V_GS| > |V_TN|, NMOS is still on. V_GD = 0 < V_TN, NMOS operates in saturation region.

   2. PMOS: |V_GS| > |V_TP|, PMOS is still on. V_GD = 0 > V_TP, PMOS operates in saturation region.

4. V_inv < V_in < V_DD - |V_TP| -> 0.5 < V_in < 0.6V. Let's take V_in = 0.55V and assume V_out is 0.2V.

   1. NMOS: |V_GS| > |V_TN|, NMOS is ON. V_GD = 0.35V > V_TN, NMOS operates in linear region.

   2. PMOS: |V_GS| > |V_TP|, PMOS is ON. V_GD = 0.35V > V_TP, PMOS operates in saturation region.

5. V_DD - |V_TP| < V_in < V_DD -> 0.6 < V_in < 1. Let's take V_in = 0.75V and assum V_out is 0V.

   1. NMOS: |V_GS| > |V_TN|, NMOS is ON. V_GD = 0.75V > V_TN, NMOS operates in linear region.

   2. PMOS: |V_GS| < |V_TP|, PMOS is OFF.

V_in is the gate voltage V_G here.

The above calculation is based on the following table we have introduced in Lec 01. As for the CMOS inverter case,

• For NMOS: V_gsn = V_in, V_dsn = V_out.

• For PMOS: V_gsp = V_in - V_DD, V_dsn = V_in - V_DD.

To summarize the five regions of operations together into one image, we have the following VTC of CMOS inverter

Now, we can draw the short-circuit current (I_inv) vs. Vin graph, and it looks like as follows,

From the graph above, we can see that the CMOS seems to only consume power when switching.

However, as I use "seems to" above, means that in reality, due to sub-threshold currents, etc, there is still some power consumption when the CMOS inverter is in OFF state.

Inverter with a Load

Normally, CMOS inverter will have parastic resistances and capacitances attached to the output node. Hence principle of operation of inverter alters a bit. This reflects in the appearnce of rise time (t_r), fall time (t_f), ..., we have introduced in Lec 01.

These time delays appear because charging and discharging the capacitor attached to the output node takes time! (CG1111A again!)

Charging the load

When V_in = 0V, the PMOS will turn on the current will flow from V_DD, through the PMOS device (it has on resistance!) and finally through the capacitor to charge it until the capacitor is fully charged.

That's why PMOS device is called pull-up device.

Discharging the load

After the capacitor is fully charged, it has the polarity shown as above. Now, if V_in = 1, our PMOS will be turned off and NMOS will be turned ON, forming a circuit so that the current can flow from the capacitor, through the NMOS device, and lastly to the ground until the capacitor is finally discharged.

That's why NMOS device is called pull-down device.

Transient Response

As it takes time to charge and discharge the capacitor, we can do the transient analysis to get a formula for calculating t_pLH (when charging) and t_pHL (when discharging).

For an RC circuit, the capacitor voltage at time $t$ is given by

$$V(t)=V_{\text{DD}}\cdot e^{-t/RC}$$

Recall that when we are doing the t_pLH and t_pHL calculation, we are only interested in the 50% point. So

• When charging, t_pLH is the time taken for Voltage across the capacitor to go from 0 -> V_DD/2.

• When discharging, t_pHL is the time taken for Voltage across the capacitor to go from V_DD/2 -> 0.

Thus, we can plug V(t) = V_DD/2 into our formula and solve for $t$

$$\begin{align*}\frac{V_{\text{DD}}}{2}&=V_{\text{DD}}\cdot e^{-t/RC}\\ t&=\ln2\cdot R\cdot C\\t&\approx0.69\cdot R\cdot C\end{align*}$$

where $R$ is the on resistance of the PMOS/NMOS device, and $C$ is the capacitance of the capacitor.

Hence, a fast gate is built either by keeping the output capacitance small or by decreasing the on-resistance of the transistor.

There is also a second approach to know the propagation delay if we don't know the on-resistance, it is introduced later.

Power Dissipation

As we have seen above, when the CMOS is switching, the short circuit current will consume some power. Also, we have mentioned about the leakage current, which will also consume some power. Lastly, as we have introduced the capacitors above, charging and discharging the capacitors will also consume some power, this is called dynamic power consumption.

Dynamic Power Consumption

We have already seen the image when we are charging the capacitor,

The total energy/transition is $C_L\cdot V_{\text{DD}}^2$, and it can be calculated by integrating the following

$$E_{\text{VDD}}=\int_0^\infty i_{\text{VDD}}(t)\cdot V_{\text{DD}}~dt$$

Since $V_{\text{DD}}$ is constant, move it outside the integral:

$$\begin{align*} E_{\text{VDD}} &= V_{\text{DD}} \int_0^\infty i_{\text{VDD}}(t)~dt \end{align*}$$

For a capacitive load $C_L$, use $i_{\text{VDD}}(t) = C_L \frac{dv_{\text{out}}(t)}{dt}$ (during charging, where $v_{\text{out}}$ is the output voltage):

$$\begin{align*} E_{\text{VDD}} &= V_{\text{DD}} \int_0^\infty C_L \frac{dv_{\text{out}}(t)}{dt}~dt \end{align*}$$

Move $C_L$ outside and change variable to $v = v_{\text{out}}$ (substitute $dt = dv / (dv/dt)$):

$$\begin{align*} E_{\text{VDD}} &= V_{\text{DD}}\cdot C_L \int_0^{V_{\text{DD}}}1~dv \end{align*}$$

Evaluate the integral (limits from 0 to $V_{\text{DD}}$ as $v_{\text{out}}$ charges fully):

$$\begin{align*} E_{\text{VDD}} &= V_{\text{DD}} \cdot C_L \cdot V_{\text{DD}} = C_L V_{\text{DD}}^2 \end{align*}$$

Its power is energy/transition times frequency f, which is $C_L\cdot V_{\text{DD}}^2\cdot f$. However, we can see the in this circuit, the capacitor will also take some power consumption, and it can be calculated by integrating the follwoing, which will give us $\frac{1}{2}\cdot C_L\cdot V_{\text{DD}}^2$,

$$E_{C_L}=\int_0^\infty i_{\text{VDD}}(t)\cdot v_{\text{out}}~dt$$

Similarly as above, for a capacitive load $C_L$, use $i_{\text{VDD}}(t) = C_L \frac{dv_{\text{out}}(t)}{dt}$ (during charging, where $v_{\text{out}}$ is the output voltage):

$$\begin{align*} E_{C_L} &= \int_0^\infty C_L \frac{dv_{\text{out}}(t)}{dt} \cdot v_{\text{out}}(t)~dt \end{align*}$$

Move $C_L$ outside the integral:

$$\begin{align*} E_{C_L} &= C_L \int_0^\infty v_{\text{out}}(t) \cdot \frac{dv_{\text{out}}(t)}{dt}~dt \end{align*}$$

Substitute $v = v_{\text{out}}$, so $dv = \frac{dv_{\text{out}}}{dt}dt$, and change the limits of integration from $t: 0 \to \infty$ to $v: 0 \to V_{\text{DD}}$ (as $v_{\text{out}}$ charges from 0 to $V_{\text{DD}}$):

$$\begin{align*} E_{C_L} &= C_L \int_0^{V_{\text{DD}}} v~dv \end{align*}$$

Evaluate the integral:

$$\begin{align*} \int_0^{V_{\text{DD}}} v~dv &= \left[ \frac{1}{2} v^2 \right]_0^{V{\text{DD}}} = \frac{1}{2} V_{\text{DD}}^2 - 0 = \frac{1}{2} V_{\text{DD}}^2. \end{align*}$$

Thus, the final result is:

$$\begin{align*} E_{C_L} &= C_L \cdot \frac{1}{2} V_{\text{DD}}^2 = \frac{1}{2} C_L V_{\text{DD}}^2 \end{align*}$$

But this is only half of the total energy consumption. Where does the rest half go? If you think about it, it won't be hard to find out that the other half is dissipated as heat on the PMOS's resistor.

The above analysis is based on the PMOS! In other words, when we are charging! When we are discharging, the energy consumption from the power supply is 0J! And all the energy stored in the capacitor ($\frac{1}{2}\cdot C_L\cdot V_{\text{DD}}^2$) will dissipate as heat on the NMOS's resistor.

Modification for Circuits with Reduced Swing

As we have seen above, we can exploit reduced swing to lower the power. And the circuit after modification is shown below,

And now the energy per transition will be $E_{0 \to 1} = C_L \cdot V_{\text{dd}} \cdot (V_{\text{dd}} - V_t)$ and the energy for the capacitor will be $\frac{1}{2}\cdot C_L\cdot (V_{\text{DD}}-V_t)^2$.

We can just change the upper limit from $V_{\text{DD}}$ to $V_{\text{DD}}-V_t$ to get the above result. The integration processes are exactly the same.

Node Transition Activity and Power

Now, let's consider switching a CMOS gate for $N$ clock cycles

$$E_N = C_L \cdot V_{\text{dd}}^2 \cdot n(N)$$

where $E_N$ is the energy consumed for $N$ clock cycles and $n(N)$ is the number of $0\to1$ transitions in $N$ clock cycles. Thus, we can have the average power $P_{\text{avg}}$ as follows,

$$\begin{align*} P_{\text{avg}} &= \lim_{N \to \infty} \frac{E_N}{N} \cdot f_{\text{clk}} = \left( \lim_{N \to \infty} \frac{n(N)}{N} \right) \cdot C_L \cdot V_{\text{dd}}^2 \cdot f_{\text{clk}} \end{align*}$$

We can further define the activity factor $\alpha_{0\to1}$ as follows,

$$\begin{align*} \alpha_{0 \to 1} &= \lim_{N \to \infty} \frac{n(N)}{N} \end{align*}$$

And now, we can rewrite our average power $P_{\text{avg}}$ as follows,

$$\begin{align*} P_{\text{avg}} &= \alpha_{0 \to 1} \cdot C_L \cdot V_{\text{dd}}^2 \cdot f_{\text{clk}} \end{align*}$$

CMOS Inverter Propagation Delay

In the Transient Response analysis, we have already seen how to calculate the propagation delay of a CMOS inverter when we know the NMOS/PMOS on-resistance as well as the capacitance $C_L$. Now, we introduce the second method to know the propagation delay if we don't know the on-resistance, but know the average current I_av in the circuit.

Starting with $i = C \frac{dv}{dt}$, move $dt$ to the L.H.S and integrate both sides:

$$\begin{align*} i ~ dt &= C ~ dv \end{align*}$$

Integrate from initial to final conditions, where $v$ goes from $v_1$ to $v_2$ and time $t_p$ is the propagation delay:

$$\begin{align*} \int_0^{t_p} i(t)~dt &= \int_{v_1}^{v_2} C~dv \end{align*}$$

Since $C = C_L$ is constant, factor it out:

$$\begin{align*} C_L \int_0^{t_p} i(t)~dt &= C_L \int_{v_1}^{v_2}1~dv \end{align*}$$

The right-hand side integrates to the voltage difference:

$$\begin{align*} C_L \int_0^{t_p} i(t)~dt &= C_L (v_2 - v_1) \end{align*}$$

The left-hand side represents the charge transferred, and since $I_{\text{av}} = \frac{1}{t_p} \int_0^{t_p} i(t)~dt$, substitute $I_{\text{av}} \cdot t_p$:

$$\begin{align*} I_{\text{av}} \cdot t_p &= C_L (v_2 - v_1) \end{align*}$$

Solve for $t_p$:

$$\begin{align*} t_p &= \frac{C_L (v_2 - v_1)}{I_{\text{av}}} \end{align*}$$

For the high-to-low propagation delay $t_{\text{PHL}}$, $v_2 - v_1 = V_{\text{swing}}$ (full swing from $V_{\text{DD}}$ to 0, but noting $t_p$ is 50% of full swing), so we have:

$$t_{\text{PHL}} = \frac{C_L V_{\text{swing}}/2}{I_{\text{av}}}$$

Load Capacitance / Resistance

Load Capacitance

When a CMOS gate drives another CMOS gate, the driver "sees" a capacitive load. The load capacitance consists of

1. gate capacitance of the load from two MOSFETS on the right (C_g)

2. junction capacitance from common drain of the driver inverter on the left (C_j), and

3. the parastic routing capacitance from the metal line used for connection (C_w)

In other words, the load capacitcance is

$$C_L=C_g+C_j+C_w$$

Transistor

1

Gate Capacitance

Gate capacitances estimation in different regions is below. However many times a constant value is used.

Parameter	Off	Linear	Saturation
$C_{gb}$	$\frac{\epsilon_{sio_2} A}{t_{ox}}$	0	0
$C_{gs}$	0	$\frac{\epsilon_{sio_2} A}{2t_{ox}}$	$\frac{2\epsilon_{sio_2} A}{3t_{ox}}$
$C_{gd}$	0	$\frac{\epsilon_{sio_2} A}{2t_{ox}}$	0

In this table, $\epsilon_{sio_2}=\epsilon_o\cdot\epsilon_v$, and $A$ is the area, which is the same as $W\cdot L$.

2

Wire Capacitance

$$C_{\text{wire}}=C_{pp}+C_{\text{fringe}}$$

$C_{pp}$ is the same as $C_{\text{area}}$, which can be calculated using

$$C_{\text{area}}=C_{\text{per unit area}}\cdot W\cdot L \tag{1}$$

where, $C_{\text{per unit area}}=\frac{\epsilon}{t}$, and $\epsilon$ is the electron mobility and $t$ is the thickness. However, the $C_{\text{per unit area}}$ will usually be given.

The Eq. (1) applies to any capacitance calculation.

Load Resistance

To calculate the resistance, we can use the following formula

$$R=\frac{\rho\cdot L}{H\cdot W}$$

where we treat $\frac{\rho}{H}$ as a whole and name it as sheet resistance with the unit ( $\Omega/\square$) and $\frac{L}{W}$ has the unit of $\square$ and they must be converted to the same unit before the division!