Lab 01
Introduction
What is an FPGA?
Strictly speaking, the term FPGA is used to refer to the chip on, say, our Nexys 4 board — the one in the center which says "Artix-7" on it. The Nexys 4 as a whole is an FPGA development board. Sometimes, we may refer to the whole board as an "FPGA" - this is technically incorrect. Similarly, an Arduino is a microcontroller development board, not a microcontroller; the Atmega 328P chip on the Arduino is the microcontroller.
The FPGA Design Flow
Write RTL code in HDL
Register-Transfer Level (RTL) code is written in an HDL. It describes the system we want to design in terms of the logic we want it to represent. Of course, the first step in creating a design is to write the RTL code so that we can eventually put it on our FPGA.
Simulate RTL code
This is an extremely important step in the FPGA design flow. Unfortunately, it is also one that is super tempting to skip! As a designer, it is extremely important for us to use the simulator to make sure our design is logically correct before we proceed to the next steps. If we decide to skip simulation and testing, we risk building and uploading a full design that produces the wrong output — with larger designs, this could be hours or days wasted!
Synthesis
Synthesis takes our RTL code and turns it into a "netlist" - that is, it converts it into a set of connections between the different components available on our FPGA board.
Implementation
Implementation takes our synthesised netlist and decides how the FPGA should be configured to implement that netlist. For example, it will choose the specific components to be used on the board (placement), and the specific wires that should be used to connect these components (routing).
Programming/Uploading
After running implementation, we need to generate a bitstream — this is a file we can upload to our FPGA board to program the FPGA and implement our design on it. Then, we upload the bitstream to our FPGA board, and voila: we have a working design on our FPGA!
Creating a new Project in Vivado
Constraints
Constraints files tell Vivado about the features of your FPGA board and how all of its peripherals like the LEDs and switches are connected to the FPGA chip. Therefore, every FPGA board has a different constraints file, and you must choose the correct one for your board. In our case, we are using a Nexys 4, so click "Add Files" and then add the file Nexys-4-Master.xdc.
Simulation in Vivado
We mentioned above that simulation is an important step in the FPGA design flow. Behavioral simulation (the kind we will use) is perhaps the most important for us — it allows us to verify that our logic is all correct.
Testbench
As we have seen in our textbook, we now explain testbench using another way.
The simulation testbench is an environment where we connect the device we want to test, to inputs that we can control and to outputs that we can monitor.
Writing a testbench
In this section, there is one line of error code that needs us to debug. The error code lies in line 44 of Adder.sv. Basically, just change the index at the R.H.S from 2 to 3.
Making our design work
Setting up constraints
As we will also need to use led[8:0] in this project, we should uncomment the line 64-91 in our constraint file — Nexys-4-Master.xdc.
Generate the bitstream
After generating the bitstream and program my FPGA, this is what I get for Question 4. Great! It works! Yay! ☺️
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