FPGA Design Tips

RTL Coding Steps

Theoretical

This part has been introduced in Lec 02! Why theoretical, I guess it's because it is introduced during the lec. 😂 But that doesn't mean it's not important, it's still very important!

Practical

We have introduced the FPGA Design Flow in CS2100DE Lab 01. Here, I want to add more steps when we write our RTL Code.

1

Know your design specification

Before we write anything, clarify our design specification, which is mainly about

1. what inputs we will use -> how we will control our FPGA board

   1. What buttons will be used? (btnR, btnC, etc)

   2. What switches will be used? (sw[2:0], etc)

2. what outputs we will use -> how we want to display on our FPGA board

   1. Is it the seven-segment display? (an[7:0], seg[6:0])

   2. Is it the LED? (led[2:0], etc)

These are the very important things we need to clarify before actually writing our FPGA code.

These inputs and outputs are then specified in our Top.sv or Top.v module.

2

Design the inner logic

In Verilog, the simplest buliding is called modules. Our top module is Top.sv / Top.v, and it is composed of many other instantiated small modules, this is called structural modeling. In this step, we mainly care about

1. How each small module interact with others and our top module's inputs/outputs.

Define new variables or new combinational/sequential logic if it is necessary.

This step should also be done in our top module Top.sv or Top.v.

3

Make the smaller module as flexible as possible

In structural modeling, the smaller modules are used very often. Thus, it will be a good idea to make them as flexible as they can, by parameterizing the modules.

A more concrete example about parameterized module is here.