Latches and Flip-Flops

Bistable Element

The fundamental building block of memory is a bistable element, an element with two stable states. Figure 3.1 (a) shows a simple bistable element consisting of a pair of inverters connected in a loop. Figure 3.1 (b) shows the same circuit redrawn to emphasize the symmetry.

The inverters are cross-coupled, meaning that the input of I1 is the output of I2 and vice versa. The circuit has no inputs, but it does have two outputs, $Q$ and $\bar Q$.

Analyzing this circuit is different from analyzing a combinational circuit because it is cyclic: $Q$ depends on $\bar Q$ and $\bar Q$ depends on $Q$. So, we just need to consider two cases: $Q$ is 0 or $Q$ is 1.

And we may find out that this circuit is stable under these two cases (By saying the circuit is stable, we mean that under each of the two cases above, $Q$ and $\bar Q$ don't conflict). Thus, we can say this cross-coupled inverter has two stable states, and because of this, it is bistable.

Notes

1. An element with N stable states conveys $\log_2N$ bits of information, so a bistable element stores one bit.

2. The state of the cross-coupled inverters is contained in one binary state variable, $Q$. The value of $Q$ tells us everything about the past that is necessary to explain the future behavior of the circuit. Specifically, if $Q$ = 0, it will remain 0 forever, and if $Q$ = 1, it will remain 1 forever.

3. The circuit does have another node, $\bar Q$, but $\bar Q$ does not contain any additional information because if $Q$ is known, $\bar Q$ is also known. On the other hand, $\bar Q$ is also an acceptable choice for the state variable.

4. When power is first applied to a sequential circuit, the initial state is unknown and usually unpredictable. It may differ each time the circuit is turned on.

Although the cross-coupled inverters can store a bit of information, they are not practical because the user has no inputs to control the state. However, other bistable elements, such as latches and flip-flops, provide inputs to control the value of the state variable. The remainder of this section considers these circuits.

SR Latch

One of the simplest sequential circuits is the SR Latch, which is composed of two cross-coupled NOR gates, as shown in Figure 3.3. The latch has two inputs, S and R, and two outputs $Q$ and $\bar Q$. The SR latch is similar to the cross-coupled inverters, but its state (the value of $Q$ ) can be controlled through the S and R inputs, which set and reset the output $Q$.

To analyze this circuit, we can build a truth table by considering the four cases of two inputs S and R. And we will build a truth table as shown in Figure 3.5 below

Note that in Case IV, when S and R are both 0, there are only two subcases which the current $Q$ can be either 0 or 1. Thus, we find that the future $Q$ will still remain the same.

The SR latch is represented by the symbol in Figure 3.6. Using the symbol is an application of abstraction and modularity.

Like the cross-coupled inverters, the SR latch is a bistable element with one bit of state stored in $Q$. Notice that the entire history of inputs can be accounted for by the single state variable $Q$.

D Latch

The SR Latch is awkward because it behaves strangely when both S and R are simultaneously asserted. Moreover, the S and R inputs conflate the issues of what and when. And designing circuits becomes easier when these questions of what and when are separated. The D latch in Figure 3.7 (a) solves these problems. It has two inputs:

1. The data input, D, controls what the next state should be.

2. The clock input, CLK, controls when the state should change.

By analyzing this circuit, we see that the clock controls when data flows through the latch. When CLK = 1, the latch is transparent. The data at D flows through to Q as if the latch were just a buffer (from the point of comparing output Q and input D). When CLK = 0, the latch is opaque. It blocks the new data from flowing through to Q, and Q retains the old value. Hence, the D latch is sometimes called a transparent latch or level-sensitive latch. The D latch symbol is given in Figure 3.7 (c).

In the D latch, from the truth table, we can clearly see that its state variable is still $Q$. And the D latch is actually built upon the SR latch!

We may notice that the D latch updates its state continuously while CLK = 1. We shall see later in this chapter that it is useful to update the state only at a specific instant in time.

Types of Latches

The latches can be classified into two types:

1. Transparent High:

   1. When CLK is HIGH (1): The latch is Transparent. The output Q follows the input D immediately (changes in D are seen at Q).

   2. When CLK is LOW (0): The latch is Opaque (Latched). The output Q freezes and holds the last value it had right before the clock went low.

2. Transparent Low:

   1. When CLK is LOW (0): The latch is Transparent. The output Q follows the input D immediately.

   2. When CLK is HIGH (1): The latch is Opaque (Latched). The output freezes.

D Flip-Flop

A D flip-flop can be built from two back-to-back D latches controlled by complementary clocks, as shown in Figure 3.8 (a). The first latch, L1, is called the master. The second latch, L2, is called the slave. The node between them is named N1. A symbol for the D flip-flop is given in Figure 3.8 (b). When the $\bar Q$ output is not needed, the symbol is often condensed as in Figure 3.8 (c).

To analyze the behavior of a D flip-flop, we can see the following example (ignoring the delay between the gates 😂),

To put it simply, a D flip-flop copies D to Q on the rising edge of the clock, and remembers its state at all other times until the next rising edge comes, then it will update its state.

The sentence above is very very important! And beginner digital designer must remember it!

The rising edge of the clock is often just called the clock edge for brevity. The D input specifies what the new state will be. The clock edge indicates when the state should be updated.

A D flip-flop is also known as a master-slave flip-flop, an edge-triggered flip-flop, or a positive edge-triggered flip-flop. The triangle in the symbols denotes an edge-triggered clock input. The $\bar Q$ is often omitted when it is not needed.

The term flip-flop or latch by itself usually refers to a D flip-flop or a D latch, respectively, because these are the types most commonly used in practice. We will use this convention through this book.

Enabled Flip-Flop

An enabled flip-flop adds another input called EN or ENABLE to determine whether data is loaded on the clock edge. When EN is TRUE, the enabled flip-flop behaves like an ordinary D flip-flop. When EN is FALSE, the enabled flip-flop ignores the clock and retains its state.

Enabled flip-flops are useful when we wish to load a new value into a flip-flop only some of the time, rather than on every clock edge.

Figure 3.10 shows two ways to construct an enabled flip-flop from a D flip-flop and an extra logic.

• In Figure 3.10 (a), a multiplexer chooses whether to pass the value at D , if EN is TRUE, or to recycle the old state from Q, if EN is FALSE. (The EN here acts as the select line for the multiplexer).

• In Figure 3.10 (b), the clock is gated (with an AND gate), this is not recommended because the gate can delay the clock and cause timing errors!

The symbol for an enabled flip-flop is given in Figure 3.10(c).

Resettable Flip-Flop

A resettable flip-flop adds another input called RESET. When RESET is FALSE, the resettable flip-flop behaves like an ordinary D flip-flop. When RESET is TRUE, the resettable flip-flop ignores D and resets the output to 0.

Resettable flip-flops are useful when we want to force a known state (i.e., 0) into all the flip-flops in a system when we first turn it on.

Such resettable flip-flops maybe synchronously or asynchronously resettable.

• Synchronously resettable flip-flops reset themselves only on the rising edge of CLK.

• Asynchronously resettable flip-flops reset themselves as soon as RESET becomes TRUE, independent of CLK.

Figure 3.11 (a) shows how to construct a synchronously resettable flip-flop with active low reset from an ordinary D flip-flop and an AND gate. Figures 3.11 (b) and 3.11 (c) show symbols for the resettable flip-flop with active high reset.

Asynchronous resettable flip-flops require modifying the internal structure of the flip-flop. Both synchronously and asynchronously resettable flip-flops are frequently available to the designer as standard components.

Settable Flip-Flop

As you might imagine, settable flip-flops are also occasionally used. They load a 1 into the flip-flop when SET is asserted and they, too, come in synchronous and asynchronous flavors. The symbols for settable flip-flops are just changing the "r" to "s" at the bottom of the rectangle.

Resettable and settable flip-flops may also have an enable input and may be grouped into N-bit registers.

Register

An N-bit register is a bank of N flip-flops (referring to D flip-flops) that share a common CLK input, so that all bits of the register are updated at the same time.

Registers are the key building block of most sequential circuits.

Figure 3.9 shows the schematic and symbol for a four-bit register with inputs $D_{3:0}$ and outputs $Q_{3:0}$. $D_{3:0}$ and $Q_{3:0}$ are both 4-bit buses.

Putting it all together

Latches and flip-flops are the fundamental building blocks of sequential circuits. Remember that:

1. A D latch is level sensitive, which means when the CLK is 1, the D latch will copy the input D to the output Q continuously.

2. A D flip-flop is edge-triggered, which specifically means the D flip-flop copies D to Q once on the rising edge of CLK.

For latches and flip-flops, besides the above two times, at all other times, latches and flip-flops retain their old state.

A register is a bank of several D flip-flops that share a common CLK signal.

Example: Flip-Flop and Latch Comparision

Ben bitdiddle applies the D and CLK inputs as shown in Figure 3.14 to a D latch and a D flip-flop. Help him determine the output, Q, of each device.